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NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module
32Mx72 bit One Bank Unbuffered SDRAM Module
based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
Features
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168-Pin Unbuffered 8-Byte Dual In-Line Memory Module
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Intended for PC133 applications
- Clock Frequency: 133MHz - Clock Assess Time: 5.4ns Inputs and outputs are LVTTL (3.3V) compatible Single 3.3V 0.3V Power Supply Single Pulsed RAS interface SDRAMs have 4 internal banks Module has 1 physical bank Fully Synchronous to positive Clock Edge l l l l l
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Automatic and controlled Precharge commands Programmable Operation: - CAS Latency: 2, 3 - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8 - Operation: Burst Read and Write or Multiple Burst Read with Single Write Suspend Mode and Power Down Mode 8192 Refresh cycles distributed across 64ms Gold contacts SDRAMs in TSOP Type II Package
- Clock Cycle: 7.5ns
Data Mask for Byte Read/Write control Auto Refresh (CBR) and Self Refresh
Serial Presence Detect with Write Protect
Description
NT256S72V89A0G is unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMM) which is organized as 32Mx72 high-speed memory arrays and is configured as one 32M x 72 physical bank. The DIMM uses nine 32Mx8 SDRAMs in 400mil TSOP II packages. The DIMM achieves high-speed data transfer rates of up to 133MHz by employing a prefetch / pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst power.
All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. All inputs are sampled at the positive edge of each externally supplied clock (CK0, CK2). Internal operating modes are defined by combinations of RAS , CAS , WE , S0 / S2 , DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 15-bit address bus accepts address information in a row / column multiplexing arrangement. Prior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the customer.
Ordering Information
Part Number
NT256S72V89A0G-7K
NT256S72V89A0G-75B
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Organization MHz. 143MHz 133MHz 133MHz 32Mx72 100MHz 125MHz 2 3 2 2 3 2 2 3 2 CL 3 2 3 t RCD 3 2 3 t RP 3 2 3
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Speed
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Leads
Power
Gold
3.3V
NT256S72V89A0G-8B 100MHz * CL = CAS Latency
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Pin Description
CK0, CK2 CK1, CK3 CKE0 Clock Inputs Unused (terminated) Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address Inputs DQ0-DQ63 CB0-CB7 DQMB0-DQMB7 VDD VSS NC SCL SDA SA0-2 WP Data input/output Check Bit Data input/output Data Mask Power (3.3V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial Presence Detect Write Protect Input
RAS CAS
WE
S0 , S2
A0-A9, A11, A12 A10 / AP BA0, BA1
Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQMB1 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQMB5 NC Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC SA0 SA1 SA2 VDD
S0
NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD CK0 VSS NC
RAS
VSS A1 A3 A5 A7 A9 BA0 A11 VDD *CK1 A12 VSS CKE0 NC DQMB6 DQMB7 NC VDD NC NC CB6 CB7 VSS DQ48 DQ49
S2
DQMB2 DQMB3 NC VDD NC NC CB2 CB3 VSS DQ16 DQ17
WE
DQMB0
CAS
DQMB4
Note: All pin assignments are consistent for all 8-byte unbuffered versions. Check bits (CB0-CB7) are applicable only to the x72 DIMM; *CK1 and CK3 are terminated .
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module SDRAM DIMM Block Diagram (1 Bank, 32Mx8 SDRAMs)
S0 DQMB0
* DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
DQMB4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
D0
D5
DQMB1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
DQMB5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
D1
D6
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS
D2
S2 DQMB2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
DQMB6
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
D3
D7
DQMB3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
DQMB7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SPD DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS
D4
D8
RAS CAS CKE0 WE A0-A12 BA0 BA1 CK0 CK2
RAS : SDRAMs D0-D8 CAS : SDRAMs D0-D8 CKE0 : SDRAMs D0-D8 WE : SDRAMs D0-D8 A0-A11 : SDRAMs D0-D8 BA0 : SDRAMs D0-D8 BA1 : SDRAMs D0-D8
SCL WP 47k A0 SA0 VDD VSS A1 A2 SDA
SA1 SA2 D0 - D8 CK1,CK3 10pF D0 - D8
0.33uF
0.1uF
CLK : SDRAMs D0-D2, D5-D6, 3.3pF Cap. CLK : SDRAMs D3-D4, D7-D8, 3.3pF Cap.
* All resistor values are 10 ohms except as shown.
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Input/Output Functional Description
Symbol CK0 , CK2 Type Input Signal Pulse Polarity Positive Edge Active CKE0 Input Level High Active their associated clock. Activates the SDRAM CK0 and CK2 signals when high and deactivates them when low. By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the Self-Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands Low Active are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS , CAS , WE define the operation to be executed by the SDRAM. Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) A0 - A9 A10/AP A11, A12 Input Level when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63, CB0 - CB7 Input Level /Output Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. The Data input/output mask places the DQ buffers in a high impedance state when Active DQMB0 -DQMB7 Input Pulse High sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a byte mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. SA0 - SA2 Input Input SDA /Output Level Level Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a pull-up resistor is required on the system board. Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM. SCL Input Pulse Since the SCL signal is inactive in the "high" state, a pull-up resistor is recommended on the system board. Active WP Input Level High VDD , VSS Supply Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited. On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied to ground through a 47K ohm pull-down resistor. Power and ground for the module. Function The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
S0 , S2
Input
Pulse
RAS , CAS , WE
BA0, BA1
Input
Pulse Low
Input
Level
-
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Absolute Maximum Ratings
Symbol VDD VIN VOUT TA TSTG PD IOUT Parameter Power Supply Voltage Input Voltage Output Voltage Operating Temperature (ambient) Storage Temperature Power Dissipation Short Circuit Output Current Rating -0.3 to +4.6 -0.3 to VDD +0.3 -0.3 to VDD +0.3 0 to +70 -55 to +125 9 50 V 1 Units Notes
C C
W mA
1 1 1 1
1.1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (T A =0 to 70 C)
Rating Symbol VDD VIH VIL VOH VOL I IL 1. 2. 3. Power Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage current Parameter Min. 3.0 2.0 -0.3 2.4 -10 Typ. 3.3 Max. 3.6 VDD + 0.3 0.8 0.4 10 V V V V V uA 1 1,2 1,3 Units Notes
All voltages referenced to VSS . VIH (max) = VDD / VDDQ + 1.2V for pulse width 5ns VIL (min) = VSS / VSSQ - 1.2V for pulse width 5ns .
Capacitance (T A =25 C , f =1MHz, V DD =3.3 0.3V)
Symbol CI1 CI2 CI3 CI4 CI5 CI6 CIO1 CIO2 Parameter Input Capacitance (A0-A9, A10/AP, A11, BA0, BA1, RAS , CAS , WE ) Input Capacitance (CKE0) Input Capacitance ( S0 - S2 ) Input Capacitance (CK0 - CK3) Input Capacitance (DQMB0 - DQMB7) Input Capacitance (SA0 - SA2, SCL, WP) Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) Input/Output Capacitance (SDA) Max. 77 58 33 40 21 9 10 11 pF Unit
DC Output Load Circuit
3.3 V 1200 ohms Output 50 pF 870 ohms VOH(DC) = 2.4V,IOH= -2mA VOL(DC) = 0.4V,IOL= -2mA
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Operating, Standby, and Refresh Currents (TA =0 to 70 C , VDD =3.3 0.3V)
Parameter Symbol Test condition - 7K 1 bank operation , tRC = tRC(mim), tCK = min Operating current ICC1 Active-Precharge Command cycling without burst operation Precharge standby current in power-down mode ICC2PS CKE0 VIL (max), tCK = min, ICC2P 16 16 16 mA 1170 1080 1035 mA 1, 2 Speed - 75B - 8B Unit Note
S0 , S2 = VIH (min)
CKE0 VIL (max), tCK =o , o 16 16 16 mA
S0 , S2 = VIH (min)
CKE0 VIH (min), tCK = min 270 270 180 mA 3
Precharge standby current in non power-down mode
ICC2N
S0 , S2 = VIH (min)
ICC2NS CKE0 VIH (min), tCK =o , o 72 72 72 mA 4
S0 , S2 = VIH (min)
ICC3P CKE0 VIL (max), tCK =min. 54 54 54 mA 5
No Operating current ( Active state : 4 bank)
S0 , S2 = VIH (min)
ICC3N
(Power Down Mode) 540 540 360 mA 3
CKE0 VIH (min), tCK =min
S0 , S2 = VIH (min)
Operating current ( Burst mode ) Auto(CBR) refresh current Self refresh current Serial PD Device Standby Current Serial PD Device Active Power Supply Current signals are changed up to three times during t RC (min). 2. The specified values are obtained with the output open. 3. Input signals are changed once during three clock cycles. 4. Input signals are stable. 5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ). 6. Input signals are changed once during t ck(min) . 7. VDD =3.3V 8. Input pulse levels VDD x 0.1 to VDD x 0.9, input rise and fall times 10ns, input and output timing levels VDD x 0.5, output load 1 TTL gate and CL=100pF. ISB VIN = GND or VDD 30 30 30 ICC5 ICC6 tCK =min, CBR command cycling CKE0 0.2V 1575 27 1575 27 1395 27 mA mA A 7 ICC4 tCK =min , Read/ Write command cycling, 1080 Multiple banks active, gapless data, BL=4 1080 810 mA 2, 6
ICCA
SCL Clock Frequency=100 MHz
1
1
1
A
8
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t CK and t RC . Input
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module AC Characteristics (TA =0 to 70 C , VDD =3.3 0.3V)
1. An initial pause of 200us,with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIH and VIL ). 3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit between VIH and VIL (or between VIL and VIH ) in a monotonic manner. 4. AC timing tests have VIL =0.8Vand VIH = 2.0 V with the timing referenced to the 1.40V crossover point. 5. AC measurements assume t T =1.2 ns.
AC Output Load Circuits
tT Clock tSETUP Input tAC tLZ Output 1.4V tHOLD 1.4V tOH AC Output Load Circuit tCKL tCKH VIH 1.4V VIL Output Zo = 50 ohm 50 pF
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module AC Timing Parameters Clock and Clock Enable Parameters
- 7K Symbol tCK3 tCK2 tAC3(B) tAC2(B) tCKH tCKL tCES tCEH tSB tT 1. 2. Parameter Min. Clock Cycle Time, CAS Latency = 3 Clock Cycle Time, CAS Latency = 2 Clock Access Time, CAS Latency = 3 Clock Access Time, CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Clock Enable Set-up Time Clock Enable Hold Time Power down mode Entry Time Transition Time (Rise and Fall) 7 7.5 2.5 2.5 1.5 0.8 0 0.5 Max. 1000 1000 5.4 5.4 7.5 10 Min. 7.5 10 2.5 2.5 1.5 0.8 0 0.5 Max. 1000 1000 5.4 6 7.5 10 Min. 8 10 3 3 2 1 0 0.5 Max. 1000 1000 6 6 12 10 ns ns ns ns ns ns ns ns ns ns 1 1 2 2 - 75B - 8B Unit Note
Access time is measured at 1.4V. In AC Characteristics section, see notes. t CKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to V IH (min). t CKL is the pulse width of CLK measured from the negative edge to the positive edge referenced to V IL (max).
Common Parameters
- 7K Symbol tCS tCH tAS tAH tRCD tRC tRFC tRAS tRP tRRD tCCD Parameter Min. Command Setup Time Command Hold Time Address and Bank Select Set-up Time Address and Bank Select Hold Time 1.5 0.8 1.5 0.8 20 60 60 45 20 15 1 Max. 100K Min. 1.5 0.8 1.5 0.8 20 67.5 67.5 45 20 15 1 Max. 100K Min. 2 1 2 1 20 70 70 50 20 20 1 Max. 100K ns ns ns CLK 1 1 1 ns ns ns ns ns ns 1 1 - 75B - 8B Unit Note
RAS to CAS Delay
Bank Cycle Time Auto Refresh to Active/Auto Refresh Active Command Period Precharge Time Bank to Bank Delay Time
CAS to CAS Delay Time
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
- 7K Symbol tRSC Parameter Min. Mode Register Set Cycle Time 2 Max. Min. 2 Max. Min. 2 Max. CLK 1 - 75B - 8B Unit Note
1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the num ber of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Read Cycle
- 7K Symbol Parameter Min. tOH tLZ tHZ3 tDQZ Data Out Hold Time 2.7 Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 0 3 2 5.4 2.7 0 3 2 5.4 3 0 3 2 6 ns ns ns CLK 1 Max. Min. Max. Min. 2.5 Max. ns - 75B - 8B Unit Note
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
- 7K Symbol tREF tSREX Refresh Period Self Refresh Exit Time Parameter Min. 10 Max. 64 Min. 10 Max. 64 Min. 10 Max. 64 ms ns - 75B - 8B Unit Note
Write Cycle
- 7K Symbol tDS tDH tDPL tDAL3 Parameter Min. Data In Set-up Time Data In Hold Time Data input to Precharge Data In to Active Delay 5 5 5 CLK 1.5 0.8 15 Max. Min. 1.5 0.8 15 Max. Min. 2 1 15 Max. ns ns ns - 75B - 8B Unit Note
CAS Latency = 3
Data In to Active Delay tDAL2 5 0 0 CLK ns
CAS Latency = 2
tDQW DQM Write Mask Latency 0
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Serial Presence Detect -- Part 1 of 2
32Mx72 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3v SDRAMs with SPD
Byte Description -7K 0 1 2 3 4 5 6. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank Data Width of Assembly Data Width of Assembly (cont' ) Voltage Interface Level of this Assembly SDRAM Device Cycle Time at CL=3 SDRAM Device Access Time from Clock at CL=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Device Width SDRAM Device Attributes: Min CLk Delay, Random Col Access SDRAM Device Attributes: Burst Length Supported SDRAM Device Attributes: Number of Device Banks SDRAM Device Attributes: CAS Latencies Supported SDRAM Device Attributes: CS Latency SDRAM Device Attributes: WE Latency SDRAM Device Attributes 2/3 7ns 5.4ns SPD Entry Value -75B 128 256 SDRAM 13 10 1 X72 X72 LVTTL 7.5ns 5.4ns ECC SR/1x(7.8us) X8 X8 1 Clock 1,2,4,8 4 2/3 0 0 Unbuffered Wr-1/Rd Burst, Precharge All, 22 SDRAM Device Attributes: General Auto-Precharge, VDD +/10% 23 24 25 26 27 28 29 30 31 32 33 34 35 Minimum Clock Cycle at CL=2 Maximum Data Access Time from Clock at CL=2 Minimum Clock Cycle Time at CL=1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time(tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock 1.5ns 0.8ns 1.5ns 0.8ns 15ns 15ns 15ns 45ns 7.5ns 5.4ns 10ns 6ns N/A N/A 20ns 15ns 20ns 45ns 256MB 1.5ns 0.8ns 1.5ns 0.8ns Undefined 1.2A 1.2A 1.2A 12 1E 2ns 1ns 2ns 1ns 15 08 15 08 20ns 20ns 20ns 50ns 0F 0F 0F 2D 10ns 6ns 75 54 A0 60 00 00 14 0F 14 2D 40 15 08 15 08 00 12 64 12 AB 20 10 20 10 14 14 14 32 A0 60 0E 2/3 06 8ns 6ns 70 54 -8B Serial PD Data Entry (Hexadecimal) -7K -75 80 08 04 0D 0A 01 48 00 01 75 54 02 82 08 08 01 0F 04 06 01 01 00 06 80 60 -8B Note
36-61 Reserved 62 63 SPD Revision Checksum for byte 0 - 62
Checksum Data
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Serial Presence Detect -- Part 2 of 2
32Mx72 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V SDRAMs with SPD
Byte Description -7K 64-71 72 73-90 91-92 93-94 95-98 Manufacturer' JEDED ID Code s Module Manufacturing Location Module Part number Module Revision Code Module Manufacturing Data Module Serial Number N/A SPD Entry Value -75B NANYA N/A N/A N/A Year/Week Code Serial Number Undefined 100MHz CK0, CK2,CL3, CL2 Concurrent AP Undefined N/A 00 -8B Serial PD Data Entry (Hexadecimal) -7K -75B -8B 3 Note
7F7F7F0B00000000 00 00 00 yy/ww 00 00 64 AF 00 00
1,2
99-125 Reserved 126 127 Modules Supports this Clock Frequency Attributes for Clock Frequency defined in byte 126
128-255 Open for customer Use 1. 2. 3. yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) NANYA 11decimal (bank four) 0000 1011 binary 0B Hex.
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256S72V89A0G 256MB : 32M x 72 Unbuffered SDRAM Module Package Dimensions
FRONT VIEW
133.35 5.250
127.33 5.013
4.00 0.157
3.0 0.118
6.35 0.250 pin 1 66.67 2.625 42.17 1.660
6.35 0.250
Detail A
Detail B
Detail C
17.78 0.700
Side BACK VIEW
2.59 0.106 MAX.
Detail A 3.124 0.123
Detail B 3.124 0.123 0.203 0.008
Detail C 1.0 0.039
1.27 0.050
Note : All dimensions are typical unless otherwise stated. Unit : Millimeters Inches
Preliminary 09 / 2001
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
2.489 0.098
2.006 0.079
2.006 0.079
1.27 0.050
(c) NANYA TECHNOLOGY CORP.
34.925 1.375

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